ASIC Design Course [ECE413s] - Lecture (3): Verilog Overview

Video Content: 0:00 intro 03:05 Why HDL 05:40 What is Verilog 09:14 Module Structure & Port Declaration 17:36 Numeric Constants 30:11 Data Types 49:04 Verilog Primitives 52:21 Operators 1:06:15 Continuous Assignment 1:13:44 Modeling Styles 1:33:06 Procedural Assignment [Blocking & Non-Blocking] 1:45:19 Module Instantiation 1:01:34 IF Statement 2:10:04 Case Statement 2:24:29 For Loop & Disable 2:27:38 Forever, repeat & While Statements 2:28:57 Function VS Task Slides: https://drive.google.com/drive/folder... Feedback Form: https://forms.gle/FSyA7BrnF613ceBk7 LinkedIn account:   / mohamed-fares-a493a5287   #ASIC #Digital_IC_Design #verilog #fpga #icdesign #pnr #chip #vlsi #vlsidesign #vlsijobs #vlsiprojects #vlsitraining #sta #cdc #power #synthesis #area #cts #chipfactoryjob #engineering #electronics #education #floorplanning #placement #routing #verification #vhdl #HDL #fullcustom #semicustom