Carry Look-Ahead Adder 8 bit Code with Overflow in Verilog and VHDL with Testbench. Structural Model

#CLA #Carry #Look-Ahead #Adder 8 bit #Code with #Overflow in #Verilog and #VHDL with #Testbench. #Structural #modeling SV RTL code: module xor_1(s, a, b); output s; input a,b; assign s = a ^ b; endmodule // xor_1 // structural model of half_adder module half_adder(s, c, a, b); output s, c; input a, b; assign s = a ^ b; assign c = a & b; endmodule // half_adder //behavioral model of level 1 cla module l1_adder_cla_4(s, co, a, b, ci, c3); output [3:0] s; output co, c3; input [3:0] a, b; input ci; wire [3:1] c; wire [3:0] g, p; //assign g[3:0] = a[3:0] & b[3:0];//gi = ai & bi //assign p[3:0] = a[3:0] ^ b[3:0];// pi = ai xor bi half_adder a0[3:0](p, g, a, b); assign c[1] = g[0] | (p[0] & ci);//c1 = g0 + p0c0 assign c[2] = g[1] | (g[0] & p[1]) | (p[1] & p[0] & ci);//c2 = g1 + p1c1 assign c[3] = g[2] | (g[1] & p[2]) | (g[0] & p[2] & p[1]) | (p[2] & p[1] & p[0] & ci);// c3 = g2 + p2c2 assign co = g[3] | (g[2] & p[3]) | (g[1] & p[3] & p[2]) | (g[0] & p[3] & p[2] & p[1]) | (p[3] & p[2] & p[1] & p[0] & ci);// c4 = g3 + p3c3 assign s[0] = p[0] ^ ci;// si = pi xor ci //assign s[3:1] = p[3:1] ^ c[3:1]; generate for (genvar i = 1;i ＜= 3; i = i + 1) begin xor_1 myaxor2(s[i],p[i],c[i]);//works too end endgenerate assign c3 = c[3]; endmodule //structral model carry look ahead adder module adder_8(s, co, of, a, b, ci); output [7:0] s; output co, of; input [7:0] a, b; input ci; wire c3, c4, c7; l1_adder_cla_4 a0(s[3:0], c4, a[3:0], b[3:0], ci, c3 ); l1_adder_cla_4 a1(s[7:4], co, a[7:4], b[7:4], c4, c7); assign of = co ^ c7; endmodule // adder_8 VHDL RTL code: library ieee; use ieee.std_logic_1164.all; entity xor_1 is port ( s: out std_logic; a: in std_logic; b: in std_logic); end xor_1; architecture str of xor_1 is begin s＜=a xor B; end str; library ieee; use ieee.std_logic_1164.all; entity half_adder is port ( s: out std_logic; c: out std_logic; a: in std_logic; b: in std_logic); end half_adder; architecture struct of half_adder is begin s ＜= a xor b; c ＜= a and b; end struct; -- structural model of level 1 cla 4 bit library ieee; use ieee.std_logic_1164.all; entity adder_cla_4 is port ( s: out std_logic_vector(3 downto 0); co: out std_logic; a: in std_logic_vector(3 downto 0); b: in std_logic_vector(3 downto 0); ci:in std_logic; c3: out std_logic ); end adder_cla_4; architecture str of adder_cla_4 is component half_adder is port ( s: out std_logic; c: out std_logic; a: in std_logic; b: in std_logic); end component; -- component xor_1 is port ( s: out std_logic; a: in std_logic; b: in std_logic); end component; signal c:std_logic_vector(3 downto 1); signal g,p: std_logic_vector(3 downto 0); begin --g(3 downto 0) ＜=a(3 downto 0) and b(3 downto 0);--gi = ai and bi -p(3 downto 0) ＜=a(3 downto 0) xor b(3 downto 0);- pi = ai xor bi adders:for i in 3 downto 0 generate a0:half_adder port map(p(i), g(i), a(i), b(i)); end generate; c(1)＜=g(0)xor(p(0) and ci);--c1 = g0 + p0c0 c(2)＜=g(1) xor (g(0) and p(1)) xor (p(1) and p(0) and ci);--c2 = g1 + p1c1 c(3)＜=g(2) xor (g(1) and p(2)) xor (g(0) and p(2) and p(1)) xor (p(2) and p(1) and p(0) and ci);-- c3 = g2 + p2c2 co ＜=g(3) xor (g(2) and p(3)) xor (g(1) and p(3) and p(2)) xor (g(0) and p(3) and p(2) and p(1)) xor (p(3) and p(2) and p(1) and p(0) and ci);-- c4 = g3 + p3c3 s(0)＜=p(0) xor ci;-- si = pi xor ci --s(3 downto 1)＜=p(3 downto 1) xor c(3 downto 1); xors:for i in 3 downto 1 generate myxor1:xor_1 port map(s(i), p(i), c(i)); end generate; c3 ＜=c(3); end str; -- structural model of carry look ahead adder 8-bit library ieee; use ieee.std_logic_1164.all; entity adder_8 is port ( s: out std_logic_vector(7 downto 0); co: inout std_logic; off: out std_logic; a: in std_logic_vector(7 downto 0); b: in std_logic_vector(7 downto 0); ci:in std_logic); end adder_8; architecture str of adder_8 is component adder_cla_4 is port ( s: out std_logic_vector(3 downto 0); co: inout std_logic; a: in std_logic_vector(3 downto 0); b: in std_logic_vector(3 downto 0); ci:in std_logic; c3: out std_logic ); end component; signal c3, c4, c7: std_logic; begin a0: adder_cla_4 port map(s(3 downto 0), c4, a(3 downto 0), b(3 downto 0), ci, c3); a1: adder_cla_4 port map(s(7 downto 4), co, a(7 downto 4), b(7 downto 4), c4, c7); off ＜= co xor c7; end str;