MOSFET Voltage Gain: How DC Bias Controls the Amplifier

How does DC bias change MOSFET voltage gain? Work through this analog IC/RFIC interview question using square-law bias analysis, transconductance and output-node KCL. Try the free interview test via the Uplevel Engineering homepage: https://uplevelengineering.com Follow V_CTRL from Q2's DC bias to Q1's drain current and transconductance, then build the small-signal circuit and derive V_out/V_in. See why the source bypass capacitor removes Q2 from the simplified AC signal path without removing its influence on gain. The model uses identical MOSFETs in saturation, I_D = k(V_GS - V_T)^2, k = 1 mA/V² and V_T = 2 V. Channel length modulation, body effect and internal transistor capacitances are ignored. All three capacitors are ideal shorts at the RF signal frequency and open circuits for DC. No external output load is shown. The gain relationship applies within the positive V_CTRL range where both transistors remain saturated. Chapters 0:00 Circuit signals and MOSFET assumptions 0:42 Find the voltage gain 1:00 DC bias and matched-transistor current 2:17 Bias point to transconductance 2:48 Build the RF small-signal circuit 3:32 Source bypass and AC ground 4:08 Q1 small-signal model 4:29 KCL at the output node 4:55 Derive and substitute the voltage gain 5:34 How DC bias controls AC gain 5:54 Try the free interview test Topics covered: MOSFET voltage gain, DC bias, square-law drain current, transconductance, common-source amplification, source bypass capacitors, AC ground and Kirchhoff's current law. #MOSFET #AnalogIC #RFIC