Procedural continuous assignments | assign/deassign and force/release |#verilog #verification #vlsi

In this video I have covered procedural continuous assignments: Its two types are: assign-deassign force-release Explained with the help of verilog code in EDA playground Code link: https://edaplayground.com/x/KvXu 0:00 first type: assign and deassign 3:04 Example for assign and deassign 8:03 second type: force and release 10:48 Example for force and release #education #design #verilog #verification #systemverilog #sv #vlsi #semiconductor #electronics #verification #core #events #class #oops #digitalelectronics #digital #design #testbench #designverification #verilog #engineering #engineeringjobs #electronicsandcommunication #process #threads #semaphore #communicationskills