How to design a NAND logic gate at the transistor level
Mateo Aboy
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How to design a NAND logic gate at the transistor level
2 526 просмотров · 9 лет назад
Mateo Aboy
17,7 тыс. подписчиков
2 526 просмотров · 9 лет назад
This video shows how to design the topology of a NAND gate at the transistor level (using NMOS and PMOS transistors) to create a CMOS digital circuit. It shows an example of how do do combinational logic design a the transistor level.