APB vs AHB vs AXI: Bandwidth, Bursts and When to Use Each | VLSI Interview Question

Compare APB, AHB-Lite, AXI4-Lite and AXI4 across bandwidth, complexity, bursts, outstanding transactions and use cases, and know how to connect a CPU, DMA, peripherals and memory with them. 🎯 In this video • The interview question: compare APB, AHB-Lite, AXI4-Lite and AXI4 across bandwidth, complexity, bursts, outstanding transactions and use cases • Where the bandwidth comes from: APB needs a setup-then-access cycle (a word every two cycles at best), AHB-Lite overlaps the next address with current data (a word per cycle until a stall), and AXI uses independent read and write channels where addresses run ahead of data, so many requests in flight hide memory latency • A typical SoC: CPU, DMA and GPU sit on a full AXI4 fabric with the DDR controller and on-chip SRAM, while an AXI-to-APB bridge serves simple peripherals like UART, timers, interrupt registers and GPIO • How to choose: match protocol complexity to the bandwidth and concurrency a block actually needs, rather than defaulting to the fastest bus everywhere ⏱️ Chapters 0:00 Interview Question: Compare APB, AHB and AXI 1:45 Where the Bandwidth Comes From 3:28 A Typical SoC and the AXI-to-APB Bridge 5:10 Choosing the Right Protocol and Recap 🚀 Preparing for an ASIC / VLSI / digital design interview? This lecture is one of many in my Udemy course, Mastering ASIC VLSI Digital Design Interviews: clear, step-by-step explanations of the questions hiring managers actually ask, plus the follow-ups that catch candidates off guard. 👉 Get the full course at a discounted price with coupon ASIC2026: https://www.udemy.com/course/masterin... 👍 If this helped, like and subscribe for more digital VLSI interview prep, and share it with a friend who's interviewing! #AMBA #AXI #VLSI #SoCDesign