Basic NMOS Current Mirror Design |Cadence Virtuoso GPDK180 |DC, AC, Compliance Voltage, PVT & Layout

📂 GitHub Repository — Project Files 🔗 https://github.com/hemanthusarthi/cad... 📌 PROJECT INTRODUCTION This is Part 1 of 5 in a Current Mirror Family series. It covers the Basic NMOS Current Mirror: two matched NMOS transistors where a diode-connected reference device sets the gate voltage shared with the output device, so the 100 µA reference current is copied to the output branch. It serves as the baseline for comparing the Cascode, Widlar, Wilson and Current Reference circuits in the rest of the series. 🛠 TOOLS AND TECHNOLOGY • Cadence Virtuoso Schematic Editor and Layout • ADE (DC, AC and parametric analyses, PVT) • Technology: GPDK180 (180 nm CMOS), VDD = 1.8 V ⚙️ PROJECT WORKFLOW AND TECHNICAL COVERAGE • Current mirror theory and performance metrics (current accuracy, current error, compliance voltage, output resistance) • Schematic: 2 NMOS, W/L = 10 µm / 1 µm, IREF = 100 µA • DC sweep of IOUT versus VOUT (0 to 1.8 V) • AC analysis for output resistance (1/magnitude method, 1 Hz to 1 GHz) • Region of operation and compliance voltage • PVT analysis • Full-custom layout and GDS 📊 IMPORTANT SIMULATION RESULTS (IREF = 100 µA, VDD = 1.8 V) • IOUT: 99.98 µA at VDS = 724 mV • Current accuracy: 99.98% | Current error: 0.02% • Compliance voltage: approx. 300 mV • Output resistance: approx. 301.7 kΩ ⚠️ NOTES AND LIMITATIONS • All values are simulation results, not measurements from fabricated silicon. • IOUT drops at low output voltage when the output transistor leaves saturation, and the small slope in the flat region comes from channel-length modulation. 🎯 PROJECT OBJECTIVE AND AUDIENCE The goal is to understand current copying, headroom and output resistance in the simplest mirror before moving to improved topologies. Useful for ECE students, VLSI and analog IC learners, and Cadence Virtuoso beginners. 👍 If this video helped you, please LIKE and SHARE it. Questions or suggestions? Leave them in the comments. SUBSCRIBE to VLSI Works | IIIT Sri City for more VLSI and Cadence Virtuoso projects. 🎓 PROJECT CREDITS Created by: U. Hemanth Kumar Institution: IIIT Sri City Programm: ECE,UG3 #VLSI #CadenceVirtuoso #CurrentMirror #AnalogIC #CMOS #GPDK180 #180nm #AnalogDesign #OutputResistance #PVT #VLSIWorks #IIITSriCity