CSCE 611 Fall 2026 Lecture 9: RISC-V Microarchitecture 2

Topics: (1) RAM (2) RISC-V ALU (3) RISC-V Register File (4) RISC-V R-, I, and U-type (5) Lab 3 structure (6) 3-stage pipeline (7) RISC-V fetch stage (8) RISC-V execute stage (9) RISC-V writeback stage (10) Initializing program memory (11) Datapaths and control signals (12) Test program (13) Binary to base-10 conversion