ethernet part16

MAC Control Module is responsible for providing real-time flow control in a full-duplex Ethernet system by using PAUSE control frames to temporarily stop the transmission of data whenever the receiving side is unable to process incoming Ethernet frames fast enough. Its primary objective is to prevent the RX FIFO from overflowing and losing packets. The MAC Control Module is positioned between the host/CPU and the TX and RX MACs, and it contains control-frame detection, control-frame generation, a 16-bit PAUSE timer, a slot timer, and a TX/RX MAC interface. The host configures flow control through registers such as TXCTRL, CTRLMODER, TPAUSERQ, and TPAUSETV, where TPAUSERQ requests PAUSE-frame generation and TPAUSETV specifies the pause duration. A PAUSE control frame is a 64-byte minimum Ethernet frame containing a 6-byte destination address, a 6-byte source address, a 2-byte Length/Type field set to 0x8808, a 2-byte opcode set to 0x0001, a 2-byte PAUSE timer value, 42 bytes of reserved or padding data, and a 4-byte Frame Check Sequence (FCS). The destination address is generally the IEEE-defined multicast address 01-80-C2-00-00-01 or, where supported, the core's MAC address. When the RX MAC receives a frame, the MAC Control Module examines its destination address, Length/Type field, and opcode to determine whether it is a valid PAUSE frame. If the frame is not a valid control frame, it is treated as a normal Ethernet frame and passed to the upper layer; if it is a valid PAUSE frame, the module checks the RXFLOW configuration to determine whether PAUSE reception is enabled. When RXFLOW is disabled, the PAUSE frame is ignored; when enabled, the received PAUSE timer value is loaded into the timer, and the slot timer begins decrementing the PAUSE duration according to Ethernet slot-time intervals. While the PAUSE timer is nonzero, the TX MAC is prevented from transmitting new data frames, allowing the receiver to drain its FIFO and recover from congestion. When the timer reaches zero, transmission resumes automatically. The module also supports generating PAUSE frames when the local receiver experiences congestion: the host asserts TPAUSERQ and supplies the required pause time through TPAUSETV, while TXFLOW must be enabled to permit PAUSE-frame transmission. The control module waits for any currently transmitting frame to finish, generates the PAUSE frame, and sends it through the TX MAC, which adds the necessary Ethernet padding and FCS; the TX-end-frame signal indicates completion, after which the request is cleared. The TX/RX MAC interface operates transparently during normal traffic, forwarding ordinary data-frame signals directly between the host and MAC, but takes control of the TX interface when a PAUSE frame must be generated or transmission must be blocked. The RXFLOW and PASSALL configuration bits determine how received control frames are handled: depending on their combination, control frames may be dropped, stored in memory, or processed as PAUSE frames, with RXC or RXB interrupt behavior varying accordingly; when both RXFLOW and PASSALL are enabled, the diagram indicates that only the RXC interrupt is generated. The PAUSE timer is a 16-bit counter loaded with the received or configured pause value and decremented once per slot-time pulse, while the slot timer generates the timing pulse corresponding to one Ethernet slot, shown as 64 byte-times in the diagram. Verification of this module should cover valid and invalid PAUSE frames, destination-address and opcode checking, RXFLOW and PASSALL combinations, timer loading and countdown, PAUSE-frame generation, TX blocking during an active pause, automatic TX resumption at timer expiry, interrupt behavior, and normal-frame transparency. Overall, the MAC Control Module implements Ethernet link-level flow control by coordinating the host, RX MAC, and TX MAC, enabling a congested receiver to request temporary transmission suspension and thereby improving reliability by reducing RX FIFO overflow and packet loss.