Computer Architecture Lecture 2 (Arabic) | Datapath, Control, Pipelining & Hazards in MIPS

In this video, we build on the foundations introduced in Lecture 1 and go deeper into the MIPS architecture, focusing on datapath design, control logic, and the basics of pipelining. 📌 Topics covered in this lecture: Quick revision of MIPS instruction formats (R-type, I-type, J-type) Breakdown of the 32-bit instruction: opcode, registers, immediate, etc. Designing the datapath and control signals for each instruction type How to implement the JMP instruction and update control structure Introduction to pipelining and how it compares to single-cycle execution Key concepts: latency, throughput, speedup The 5 pipeline stages in MIPS (IF, ID, EX, MEM, WB) Instruction Set Architecture (ISA) considerations for pipelining Introduction to hazards: structural, data, and control Explanation of data forwarding to resolve hazards 📚 References used in this lecture: Computer Organization and Design: The Hardware/Software Interface by David A. Patterson & John L. Hennessy – 5th Edition Computer Architecture: A Quantitative Approach by John L. Hennessy & David A. Patterson – 5th Edition #ComputerArchitecture #MIPS #Datapath #Pipelining #InstructionSet #Hazards #Forwarding #PattersonHennessy #ArabicLecture #EngineeringEducation