FlagOS Unified IR: One Intermediate Representation Beyond Triton, for Every Chip Backend

Why does a Triton kernel need to be rewritten for every new chip? Recorded at the Open Compute AI Systems Forum, 2026 AI Open Compute Conference & FlagOS Tech Conference. This session walks through the FlagOS Unified IR design: Triton IR lowers into the Common IR (tile.buf dialect) via TritonToTileOp conversion; Two backend paths: a GPGPU path with warp/thread-level scheduling, and a DSA path with Tile/Core-level scheduling; Both converge into LLVM and diverse chip backends — one kernel source, many chips. A compiler-architect's view of what "unified IR" actually unifies, from programming paradigm down to scheduling granularity. #flagos #triton #ai #aicomputing #opensource #kernel