SystemVerilog Scheduling Regions, Visualized: The Stratified Event Queue

This video builds a picture of what a simulator does inside a single moment of simulation time, then it uses that picture to explain every classic race. Every result in the video is checked by a small model of the standard's scheduler (IEEE 1800-2023, clause 4.5), run in every order the standard allows. Chapters 0:00 When does a race happen? 1:46 What happens inside one moment of simulation time? 4:00 How does a flip-flop's code sit in the time slot? 6:42 Why does $display show the old value? 9:10 How does a testbench race the design, and how does a clocking block fix it? 11:02 When does an assertion see a signal 13:15 The whole time slot, start to finish Sources IEEE Std 1800-2023, IEEE Standard for SystemVerilog, clauses 4, 14, 16 and 21 (free through the IEEE GET Program) C. E. Cummings and A. Salz, SystemVerilog Event Regions, Race Avoidance & Guidelines, SNUG Boston 2006 (rev 1.2, 2007) C. E. Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!, SNUG San Jose 2000 Music: original, made for this channel