Ultra-Low-Power DTC-Based Fractional-N Digital PLL Techniques- Kenichi Okada | ESSCIRC 2019 Tutorial

Abstract: In this presentation, some design techniques for fractional-N digital PLL will be introduced to improve both jitter and power consumption for low-power wireless applications. A highly-linear and low-power DTC and TDC will be presented as well as system-level optimization. An isolated constant-slope DTC realizes 10bit 0.1mW operation with 26MHz reference clock, and sub-ps INL is achieved. The DTC-based AD-PLL achieves FoM of -246dB with 0.98mW power consumption and -56dBc worst-case fractional spur. For further power saving, duty-cycled FLL, sub-sampling/sampling switching, charge-recycling DTC, and transformer-based DCO for impedance peaking will be also explained, which achieves 0.265mw power consumption with FoM of -237dB at 2.4GHz. Finally, a DPLL-based ADC and a BLE transceiver using DPLL will be introduced. Bio: Kenichi Okada received the B.E., M.E., and Ph.D. degrees from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. He joined Tokyo Institute of Technology in 2003, and he is now Associate Professor. He has authored and co-authored more than 400 journal and conference papers. His current research interests include millimeter-wave wireless transceiver, digital PLL, and ultra-low-power RF circuits. He has worked as a TPC member of ISSCC, VLSI Circuits, and ESSCIRC, and Guest editors and Associate Editor of JSSC.