Si-Cast Ep2: Introduction to the Operating Principles of Digital Phase-Locked Loops

Digital Phase-Locked Loops (DPLLs) are fundamental blocks in modern electronic systems, from high-speed data converters to RF transceivers. But what makes a DPLL both powerful and challenging to design? In this session, we’ll dive into the operating principles behind DPLLs — exploring topics such as phase noise, digital calibration techniques, jitter optimization, and fractional-N design trade-offs. Whether you're just entering the world of PLLs or seeking to understand modern design trends, this talk will provide clarity and valuable resources for further learning. Speaker Bio: Dr. Waleed Madany (Member, IEEE) received his B.Sc. and M.Sc. degrees in electrical engineering from Aswan University in 2012 and 2017, respectively. He earned his Ph.D. from the Institute of Science, Tokyo in 2025. From 2014 to 2019, he served as a teaching assistant at Aswan University and later joined the Apple Japan Design Center as a research intern in 2023. His research focuses on time-based serial links, fully synthesizable DPLLs for frequency synthesis, clock generation, and digital calibration for mixed-signal ICs. Follow us: Facebook: https://www.facebook.com/profile.php?... LinkedIn:   / si-cast   IEEE SSCS AUSC:   / sscsalex