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Sega Model 1 MiSTer FPGA — Virtua Fighter Sega Model 1 FPGA (ALPHA)

Alphanu1

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Sega Model 1 MiSTer FPGA — Virtua Fighter Sega Model 1 FPGA (ALPHA)

370 просмотров · 4 дня назад
Alphanu1
277 подписчиков
370 просмотров · 4 дня назад
NOT A RELEASE. This is a development snapshot of a Sega Model 1 core for MiSTer. There is no sound, it does not yet run at full speed, and it is not playable. Please don't ask for a download yet. This is the first time the 3D geometry pipeline has drawn a correct frame on real hardware, so I wanted to show where it's got to. Not an emulator — RTL that behaves as the original board did, written from scratch and verified against MAME as an oracle rather than by eye. WHAT'S RUNNING • NEC V60 main CPU, executing real Virtua Racing code • Fujitsu MB86233 (TGP) geometry coprocessor, running the decapped microcode • The full 3D pipeline: matrix transform, perspective projection, backface culling, per-polygon lighting, frustum clipping, painter's-algorithm sort • Band-buffer rasterizer with span fill • The 2D tilemap layers, window/split mode and scrolling • SDRAM controller feeding seven masters • Controls read from the I/O board every frame WHAT ISN'T • No sound at all. The 68000 / YM3438 / MultiPCM board isn't started. • Runs below full speed — the CPU spends about a third of its cycles waiting on memory, and that's the current focus. • I/O board is partial, no save/NVRAM handling yet. • Only Virtua Racing has been tested. HOW IT'S VERIFIED Correctness here isn't "it looks right on screen" — it's bit-exact agreement with MAME, checked in volume: • The geometry stage walks 50 real Sega models out of the polygon ROM and compares them quad-for-quad against MAME's push_object: 836 quads, zero vertex coordinates differing. • The clipper is fuzzed against MAME's fclip_push_quad — 2,000 quads, zero disagreements. • The V60's instruction stream is diffed against MAME's from reset. • The floating-point units are fuzzed against millions of cases. THE HARDWARE DE10-Nano, Cyclone V 5CSEBA6U23I7. Currently 99% of the FPGA's logic and 100% of its block RAM — which is exactly why sound is a real problem and not just the next item on a list. Bugs found and fixed getting to this frame, in case they're useful to anyone doing similar work: the colour translation table dropped an address bit so the 3D had no blue at all; the geometry and the band sweep shared one quad store, so the whole layer vanished on every frame that built geometry and read as 50% transparent; and there was no viewport clipper, so the road's far vertices wrapped past 32,767 and drew on the wrong side of the screen.