Reading and writing timing diagrams

Understanding timing diagrams is an important part of hardware development. We'll cover the 6502 timing diagram, and see how the constraints there shape our internal FPGA design. Project CompuSAR aims at building 70's and 80's computers on a low-end FPGA. Most of the project works from scratch, and this channel half documents the progress, half teaches about the concepts that come into play when designing such a system. You can view the whole project, in sequence, in the play list here:    • Building 65c02 from scratch in Verilog: Wh...   This stage of the project is about designing the 6502 CPU on FPGA. You can watch only the 6502 videos, in sequence, at the play list here:    • Building 65c02 from scratch in Verilog: Wh...   Follow me on twitter:   / shacharshemesh   External links: w65c02 datasheet: http://westerndesigncenter.com/wdc/do... Reimplementation project: https://github.com/CompuSAR/wd65c02 Visual 6502 web site: http://visual6502.org/ Table of contents: 00:00 Intro 00:20 Modern hardware design 02:05 Timing requirements 05:21 Minimizing setup time 07:47 6502 Timing Diagram 15:22 Cycles per command 17:22 Visualizing 6502 operation 19:25 Drawing a timing diagram 24:56 Problem with the design