ethernet part14

It illustrates how the RISC CPU prepares Ethernet frames in System Memory, configures Buffer Descriptors (BDs), and enables the Ethernet MAC to transmit or receive frames using DMA, without requiring the CPU to handle every byte directly. During frame transmission, the CPU first writes the Ethernet frame into System Memory, then configures a Tx Buffer Descriptor with the frame length, memory pointer, and required control bits, and finally sets TXEN = 1 to enable transmission. The Tx DMA reads the frame from memory using the TXPNT pointer and transfers the data into the TX FIFO. When data is available, the Transmit Logic sends it to the PHY, which converts it into physical Ethernet signals and transmits it over the Ethernet Medium. The Tx Buffer Descriptor contains two main words: Word 0, at offset 0, includes the LEN field, which specifies the frame length, along with control and status bits such as RD, IRQ, WR, PAD, and CRC; Word 1, at offset 4, contains the 32-bit TXPNT memory pointer. The MAC checks the descriptor, reads the frame when the required conditions are satisfied, and updates the descriptor status after transmission. An interrupt may be generated if IRQ = 1, and the MAC may proceed to another descriptor depending on the WR and descriptor-availability conditions. The transmission example shows a 100-byte frame stored at memory address 0x80001000, with LEN = 100, TXPNT = 0x80001000, and transmission enabled using TXEN = 1. The diagram also notes that frames must be at least 4 bytes long and that padding and CRC options must be configured as required. During frame reception, the CPU prepares an empty receive buffer in memory, configures an Rx Buffer Descriptor with its buffer address, and sets E = 1 to indicate that the descriptor is empty and available for receiving a frame. It then enables reception by setting RECEN = 1. Incoming Ethernet signals travel through the PHY to the MAC Receive Logic, which processes the received data in 4-bit nibbles and passes it to the RX DMA. The RX DMA uses the RXPNTP pointer in the Rx Buffer Descriptor to store the received frame in System Memory. The Rx Buffer Descriptor also contains two main words: Word 0, at offset 0, includes LEN and reception status/control bits such as E, IRQ, WR, and CRC; Word 1, at offset 4, contains the 32-bit RXPNTP memory pointer. After the complete frame has been received and stored, the MAC updates the descriptor with the received frame length and status, and may generate an interrupt if IRQ = 1. It then advances to the next descriptor. If the next descriptor is empty (E = 1), reception can continue; otherwise, the MAC must stop receiving additional frames until a suitable buffer becomes available. The reception example shows a 512-byte frame stored at address 0x80002000, with the receive descriptor initially configured using RXPNTP = 0x80002000, E = 1, IRQ = 1, and WR = 0, followed by RECEN = 1 to enable reception. After successful reception, the descriptor reports LEN = 512 and CRC = 0, indicating no CRC error. The important notes emphasize that received frames must be at least 4 bytes long, E = 1 indicates an available receive buffer, and RECEN = 1 is required to start reception. Overall, the diagram demonstrates how the CPU, System Memory, Buffer Descriptors, DMA engines, FIFOs, Ethernet MAC, and PHY work together to transmit and receive Ethernet frames efficiently, with DMA handling the movement of frame data and the CPU managing buffer preparation, control, and status.