ethernet part9

The INT_SOURCE (Interrupt Source Register) and INT_MASK (Interrupt Mask Register) are two important 32-bit control and status registers in the OpenCores Ethernet MAC used to detect, control, and manage interrupt events between the Ethernet MAC and the CPU. The INT_SOURCE register, located at address 0x04 with a reset value of 0x00000000, records interrupt events generated during Ethernet transmission and reception, and its bits are configured as Write-1-to-Clear (W1C), meaning that software writes 1 to a particular bit to clear the corresponding interrupt, while writing 0 leaves that bit unchanged. Bits [31:7] are reserved, and bits [6:0] represent seven interrupt sources: RXC (bit 6) indicates a receive control-frame event, TXC (bit 5) indicates a transmit control-frame event, BUSY (bit 4) indicates that no free receive buffer is available and a frame may be dropped, RXE (bit 3) indicates a receive error such as CRC or alignment failure, RXB (bit 2) indicates that a frame has been received successfully, TXE (bit 1) indicates a transmit error such as a collision or timeout, and TXB (bit 0) indicates that a transmit buffer has been successfully transmitted. When an event occurs, the corresponding INT_SOURCE bit is set, allowing the CPU to identify the event by reading the register. The INT_MASK register, located at address 0x08, is also 32 bits wide and resets to 0x00000000, with bits [31:7] reserved and bits [6:0] corresponding to the same seven interrupt sources through RXC_M, TXC_M, BUSY_M, RXE_M, RXF_M, TXE_M, and TXB_M, respectively; according to the register description, a mask bit of 1 enables the corresponding interrupt, while a mask bit of 0 disables or masks it. The interrupt request signal IRQ is generated by combining the event bits in INT_SOURCE with their corresponding enable bits in INT_MASK using bitwise AND operations and then combining the results with a logical OR, conceptually expressed as IRQ = |(INT_SOURCE[6:0] & INT_MASK[6:0]); therefore, the CPU receives an interrupt when at least one event bit and its corresponding mask bit are both 1. For example, if INT_SOURCE = 0x00000004 and INT_MASK = 0x00000004, the RXB event is enabled and IRQ is asserted; if the same event occurs while its mask bit is 0, the event remains recorded in INT_SOURCE, but it does not generate an interrupt request. In a typical interrupt-handling sequence, the Ethernet MAC detects an event and sets the relevant source bit, the interrupt logic checks the corresponding mask bit, the MAC asserts IRQ if the event is enabled, the CPU enters the interrupt service routine (ISR), reads INT_SOURCE to identify the event, services the relevant operation, and writes 1 to the appropriate source bit to clear the interrupt condition. Software can configure INT_MASK to enable all interrupts by writing 0x7F, enable selected interrupts by setting only the required bits, or mask all interrupts by writing 0x00; masking an interrupt does not necessarily clear the recorded event. From a Design Verification perspective, both registers should be verified for reset values, correct read/write behavior, reserved-bit handling, individual event detection, mask enable and disable behavior, simultaneous interrupt events, correct IRQ generation, and W1C clearing without accidentally clearing unrelated events. In a UVM environment, the register model can be used to perform read/write tests and maintain expected register values, while a scoreboard checks the relationship between event generation, source-bit updates, mask settings, and the resulting IRQ signal. Assertions can verify that IRQ is asserted whenever any enabled event is pending and deasserted when no enabled event remains, subject to the design's specified timing and clearing behavior, and functional coverage can track all seven interrupt sources, enabled and masked cases, simultaneous events, and clearing scenarios. Together, INT_SOURCE records which interrupt events occurred, while INT_MASK determines which recorded events are allowed to interrupt the CPU, providing flexible and efficient interrupt management for the OpenCores Ethernet MAC.