ethernet part10

The IPGT, IPGR1, IPGR2, PACKETLEN, and COLLCONF registers are important configuration registers in the OpenCores Ethernet MAC IP core that control Ethernet frame timing, packet-length validation, collision detection, and retransmission behavior. The IPGT (Inter Packet Gap Timing) register, located at address 0x0C, controls the mandatory idle period between two consecutive Ethernet frames transmitted by the MAC in back-to-back transmission mode; it uses bits [6:0], while bits [31:7] are reserved and should be read as zero and ignored during writes. The recommended IPGT value is 0x15 for full-duplex operation and 0x12 for half-duplex operation, corresponding to the appropriate inter-packet-gap timing settings described by the IP core specification. The IPGR1 (Non-Back-to-Back Inter Packet Gap Register 1) register, located at address 0x10, defines the first part of the inter-packet-gap timing in half-duplex mode, with the recommended value 0x0C; it controls the first waiting window after a frame transmission, during which the MAC monitors carrier sense and resets or continues its timing counter according to the specified behavior. The IPGR2 (Non-Back-to-Back Inter Packet Gap Register 2) register, located at address 0x14, defines the second part of the waiting interval in half-duplex mode, with a recommended value of 0x12; after the IPGR1 window, the MAC continues counting through the IPGR2 window before allowing the next frame transmission. Together, IPGT, IPGR1, and IPGR2 help ensure that Ethernet frames are separated by the required idle periods and that the MAC handles carrier-sense conditions correctly. The PACKETLEN (Packet Length Register), located at address 0x18, configures the minimum and maximum Ethernet frame lengths using two 16-bit fields: MINFL in bits [31:16] and MAXFL in bits [15:0]. Its reset value is 0x00400600, corresponding to a minimum frame length of 64 bytes and a maximum frame length of 1536 bytes. During reception, the MAC checks whether an incoming frame satisfies the configured length limits; frames shorter than the minimum may be accepted or discarded depending on the RECSMALL setting in the MODER register, while frames exceeding the maximum may be accepted or discarded according to the HUGEN configuration. During transmission, the MAC checks the frame length and, when padding is enabled through the PAD setting, can add padding bytes to make a short frame meet the minimum length; oversized frames are handled according to the maximum-length configuration and the applicable mode settings. For example, a received 50-byte frame is below the standard 64-byte minimum and may be discarded when RECSMALL is disabled, while a 40-byte frame can be padded to 64 bytes before transmission when padding is enabled. The COLLCONF (Collision and Retry Configuration Register), located at address 0x1C, controls collision handling and retransmission behavior in half-duplex mode through the MAXRET field in bits [19:16] and the COLLVALID field in bits [5:0]; its reset value is 0x000F003F, representing a maximum retry count of 15 and a collision-valid window of 63 byte times. When a collision occurs during transmission, the MAC checks whether it falls within the configured collision-valid window: an early collision within the window triggers the collision-handling process, including incrementing the retry counter, applying the specified backoff delay, and attempting retransmission; if the retry count reaches MAXRET, the MAC reports a transmit error and stops retransmitting the frame. A collision occurring after the valid window is treated as a late collision, causing the current transmission to be aborted and reported as an error rather than being handled as a normal retryable collision. For Design Verification, these registers should be tested for reset values, register read/write behavior, reserved-bit handling, recommended configuration values, minimum and maximum packet-length boundaries, short-frame padding, oversized-frame handling, inter-packet-gap timing, carrier-sense behavior, early and late collisions, retry-counter updates, maximum retry exhaustion, and successful retransmission after backoff. A UVM testbench can use register sequences to configure the MAC, directed and constrained-random sequences to generate different frame lengths and collision scenarios, a scoreboard to compare expected frame-handling behavior with observed results, assertions to check timing and protocol requirements, and functional coverage to ensure all relevant register configurations and boundary conditions are exercised. Together, these registers ensure that the Ethernet MAC maintains proper frame spacing, validates packet sizes, and handles half-duplex collisions and retransmissions according to its configuration and the applicable Ethernet requirements.