FPGA SoC Series #2: AXI4-Lite Write IP Design

In this video, we design a custom AXI4-Lite write slave IP in Verilog and explain how a MicroBlaze processor can use an AXI4-Lite write command to control custom hardware. The lesson covers why AXI4-Lite matters in FPGA SoC design, the three phases of an AXI4-Lite write transaction, and the key signals used during the write address, write data, and write response phases. Then, we use those ideas to build a Verilog IP block that generates a one-clock-cycle start_pulse when the processor writes the correct value to the correct register address. This is Lesson #2 in the FPGA SoC series and is an important step toward building larger processor-controlled FPGA systems. In future lessons, this same AXI4-Lite start-pulse IP will be used to help control a real-time FFT design. 💻 Digital Editions (Instant Access + Discount): https://truesightlabs333.com/ 📚 Physical Editions (Amazon): 📗 Introduction to Verilog: https://www.amazon.com/dp/B0D92325VC 📘 Verilog-Based Robotics & Signal Processing: https://www.amazon.com/dp/B0F7QVT2T8 📺 Full Playlist:    • Advanced FPGA Course: Verilog Based Roboti...   ✅ Subscribe for weekly FPGA / Verilog projects as the course expands. 💎 Unlock the Full Course Experience 💎 ✔ Extended lessons ✔ Worksheets + assignments ✔ Private Discord community ✔ Lifetime access to all updates 🎓 Who This Course Is For • Electrical & Computer Engineering students • FPGA engineers seeking real project experience • Intermediate Verilog users ready for expert-level skills • Anyone preparing for a career in FPGA/ASIC hardware design ⏱️ Video Chapters 0:00 Intro 0:56 SoC Overview 1:48 AXI4-Lite Explained 6:30 Verilog Code 11:30 Block Diagram 18:30 Vitis 22:08 Promotion #FPGA #Verilog #Artix7 #ControlSystems #ADC #SignalProcessing #DigitalDesign #Robotics #digitaldesign