FPGA SoC Series #7: DDR Read with AXI DMA

In this video, we show how to use DDR memory with AXI DMA in a MicroBlaze-based FPGA system. The MicroBlaze processor first writes 16 values into DDR memory, then configures the AXI DMA to read those values from DDR and stream them into the custom AXI4-Stream receiver IP from the previous lesson. We then verify the DDR-to-stream transfer on the FPGA by using the switches to select received values and the LEDs to display them. This is Lesson #7 in the FPGA SoC series. 💻 Digital Editions (Instant Access + Discount): https://truesightlabs333.com/ 📚 Physical Editions (Amazon): 📗 Introduction to Verilog: https://www.amazon.com/dp/B0D92325VC 📘 Verilog-Based Robotics & Signal Processing: https://www.amazon.com/dp/B0F7QVT2T8 📺 Full Playlist:    • Advanced FPGA Course: Verilog Based Roboti...   ✅ Subscribe for weekly FPGA / Verilog projects as the course expands. 💎 Unlock the Full Course Experience 💎 ✔ Extended lessons ✔ Worksheets + assignments ✔ Private Discord community ✔ Lifetime access to all updates 🎓 Who This Course Is For • Electrical & Computer Engineering students • FPGA engineers seeking real project experience • Intermediate Verilog users ready for expert-level skills • Anyone preparing for a career in FPGA/ASIC hardware design ⏱️ Video Chapters 0:00 Intro 0:26 DDR & DMA 1:12 MIG Block 2:40 DMA Block 3:37 Clock Converter Block 3:53 SmartConnect Block 4:22 Reset Block 4:40 Receiver IP 4:51 Overall Block Diagram 5:09 Block Diagram Tutorial 15:50 Demonstration #FPGA #Verilog #Artix7 #ControlSystems #ADC #SignalProcessing #DigitalDesign #Robotics #digitaldesign