Differential Amplifier with ActiveLoad |Cadence Virtuoso GPDK180| Schematic to Layout,DRC, LVS & PEX

🔗 GitHub (project files, report, schematics, layout): https://github.com/vvkdev-2705/DIFF_A... In this video, I walk through the complete analog IC design flow of a single-stage Differential Amplifier with a PMOS Active (Current-Mirror) Load, implemented in Cadence Virtuoso using the GPDK180 (180 nm CMOS) technology at 1.8 V supply. 📌 What's covered: • Theory of the 5-transistor OTA topology (differential pair + active load + tail current mirror) • Hand calculations and transistor sizing (gm, Vov, ro, Ad, CMRR) • Schematic design and hierarchical symbol creation • DC operating-point analysis (all devices in saturation) • AC analysis: differential gain, common-mode gain, CMRR, bandwidth • Power analysis and transient (large-signal) response • PVT corner analysis (46 corners: FF/FS/NN/SF/SS x 3 temperatures x 3 supplies) • Monte Carlo mismatch analysis • Full-custom layout in Virtuoso Layout Suite XL • DRC and LVS verification (0 violations, schematic and layout match) • RC parasitic extraction (PEX) and post-layout simulation • Pre-layout vs. post-layout comparison 📊 Key results (nominal corner): • Differential gain (Ad): 34.81 dB (target: more than 30 dB) • CMRR: approx. 60.84 dB (target: more than 50 dB) • Bandwidth (-3 dB): 1.059 MHz (target: more than 500 kHz) • Power: 118 µW • Output swing: 1.5 V • Post-layout: gain unchanged, bandwidth 1.055 MHz (-0.4%) ⚙️ Design details: • Technology: GPDK180 (180 nm CMOS) • Supply: 1.8 V | Tail bias current: 50 µA | Load capacitance: 1 pF • Tools: Cadence Virtuoso (Schematic Editor, ADE Explorer, Layout XL), Spectre ⚠️ Design limitation: gain drops below 30 dB at the worst PVT corner and under Monte Carlo mismatch. Cascoding, longer channel length, or higher bias current can improve this. 👤 Created by: Kommi Vishal Venkat Vaibhav Institue: IIIT SriCity Programm: UG-3, ECE If you found this helpful, please like, share and subscribe. Feel free to ask questions in the comments! #VLSI #AnalogIC #CadenceVirtuoso #DifferentialAmplifier #GPDK180 #CMOS #AnalogDesign #OTA #ECE #LayoutDesign