DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD USING CROSS-COUPLED BULK IN GPDK45 | Layout, DRC, LVS & PVT

📂 *GitHub Repository — Project Files* 🔗 https://github.com/harishkumarp24-deb... Explore the available project files, design resources, and documentation in the repository. --- In this video, I present a **Differential Amplifier with Active Load Using Cross-Coupled Bulk**, designed and simulated using **Cadence Virtuoso in gpdk45 (45 nm CMOS) technology**. The project focuses on analog CMOS circuit design and characterization, including differential gain, bandwidth, common-mode rejection ratio (CMRR), power consumption, noise analysis, Monte Carlo simulation, PVT analysis, and physical layout verification. 🔧 Tools and Technology *EDA Tool:* Cadence Virtuoso *Technology:* gpdk45 — 45 nm CMOS *Simulation:* Cadence Spectre *Analysis Environment:* ADE L / ADE XL 📌 Project Workflow 1. Differential Amplifier Design Differential amplifier with active load Cross-coupled bulk technique Transistor sizing and bias current configuration Schematic design in Cadence Virtuoso 2. Circuit Simulation and Analysis Transient response DC response and DC sweep AC frequency response Differential gain analysis Common-mode gain analysis Bandwidth measurement Power consumption analysis 3. Performance Characterization Differential gain Common-Mode Rejection Ratio (CMRR) Input-equivalent noise Output-equivalent noise Power analysis 4. Monte Carlo Analysis 200-sample Monte Carlo simulation Statistical evaluation of differential gain Analysis of process variation and device mismatch 5. PVT Analysis Process corner variation Supply voltage variation Temperature variation Circuit performance under different operating conditions 6. Physical Design and Verification Pin diagram and physical layout Design Rule Check (DRC) Layout Versus Schematic (LVS) RC parasitic extraction GDS layout generation 📊 Selected Simulation Results The project report presents the following results: *Technology:* gpdk45 (45 nm CMOS) *Supply voltage:* 1 V *Differential gain:* 40.03 dB *Bandwidth:* 290 kHz *Common-mode gain:* −6.21 dB *Calculated CMRR:* 46.24 dB *Reported power consumption:* Approximately 7.64 µW *Monte Carlo analysis:* 200 samples These values are simulation results documented in the project report. Actual performance depends on the simulation setup, device models, and operating conditions. 🎯 Project Objective The objective is to design and evaluate a CMOS differential amplifier with active load and cross-coupled bulk connections, with emphasis on differential amplification, common-mode rejection, low-power operation, and robustness under process and operating variations. This project is relevant to students interested in: Analog VLSI design CMOS analog integrated circuits Differential amplifiers and active loads Cadence Virtuoso circuit simulation Analog layout and physical verification PVT and Monte Carlo analysis If you are learning analog circuit design or Cadence Virtuoso, this project demonstrates several important stages of the analog IC design workflow. 👍 Like the video if you find it useful. 💬 Leave your questions and suggestions in the comments. 🔔 Subscribe for more VLSI projects, Cadence Virtuoso tutorials, and CMOS circuit design content. 🎓 *PROJECT CREDITS* *Created by:* P. Harish Kumar *Institution:* IIIT Sri City *Department:* Electronics and Communication Engineering (ECE) #DifferentialAmplifier #CadenceVirtuoso #VLSI #AnalogVLSI #CMOSDesign #AnalogDesign #AnalogIC #45nmCMOS #gpdk45 #ActiveLoad #CrossCoupledBulk #CMRR #DifferentialGain #Bandwidth #NoiseAnalysis #MonteCarloSimulation #PVTAnalysis #Cadence #Spectre #ADEXL #ADEL #ICDesign #ChipDesign #ASICDesign #Semiconductor #TransistorSizing #CircuitSimulation #ACAnalysis #DCAnalysis #TransientAnalysis #PowerAnalysis #VLSIProjects #DRC #LVS #RCExtraction #PhysicalVerification #LayoutDesign #GDSII #ECEProjects #ElectronicsEngineering *Disclaimer:* The results presented are based on circuit simulations. They should not be interpreted as measurements from a fabricated silicon chip. CMOS differential amplifier, differential amplifier design, Cadence Virtuoso project, analog VLSI project, 45nm CMOS, gpdk45, differential amplifier with active load, cross coupled bulk, CMRR analysis, differential gain, bandwidth analysis, noise analysis, Monte Carlo simulation, PVT analysis, Cadence Spectre, analog IC design, transistor sizing, Cadence layout, DRC LVS, RC extraction, GDSII layout, VLSI project