FPGA Interview Problem: SPI Controller

This video walks through a real FPGA interview problem by designing a Verilog SPI master that reads data from an SPI-controlled ROM. The controller sends a 16-bit address to the ROM, receives the 8-bit value stored at that address, and updates its output with the received data. The lesson covers SPI Mode 0 timing, parameterized delays, state-machine design, and the Verilog implementation, followed by automated test cases and waveform verification in Vivado. 💻 Digital Editions (Instant Access + Discount): https://truesightlabs333.com/ 📚 Physical Editions (Amazon): 📗 Introduction to Verilog: https://www.amazon.com/dp/B0D92325VC 📘 Verilog-Based Robotics & Signal Processing: https://www.amazon.com/dp/B0F7QVT2T8 📺 Full Playlist:    • Advanced FPGA Course: Verilog Based Roboti...   ✅ Subscribe for weekly FPGA / Verilog projects as the course expands. 💎 Unlock the Full Course Experience 💎 ✔ Extended lessons ✔ Worksheets + assignments ✔ Private Discord community ✔ Lifetime access to all updates 🎓 Who This Course Is For • Electrical & Computer Engineering students • FPGA engineers seeking real project experience • Intermediate Verilog users ready for expert-level skills • Anyone preparing for a career in FPGA/ASIC hardware design ⏱️ Video Chapters 0:00 Intro 0:41 SPI Review 4:55 Interview Problem 5:58 Problem of Choice 13:36 Design Methodology 16:25 Code Explained 28:31 Simulation Methodology 30:35 Simulation Demo #FPGA #Verilog #Artix7 #ControlSystems #ADC #SignalProcessing #DigitalDesign #Robotics #digitaldesign